Lateral trench transistors are known; in one specific embodiment, they have a semiconductor body in which a source region and a body region, with which contact is made by means of a source contact, a drain region, with which contact is made by a drain contact, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded, are provided. Lateral current flows between the source region and the drain region along a side wall of the gate trench can be produced and controlled by means of the gate electrode.
The holes which are generated when a lateral trench transistor such as this is in the breakdown state, have to pass through the body region, which runs alongside the source region and extends over the entire trench depth, to the source contact and, if the trench depth is sufficient, the generally high layer resistance of the body region results in a high voltage drop across the area of the source region which is furthest away from the source contact. Since the body region of the lateral MOS structure (metal oxide semiconductor) also represents a base region of a parasitic npn transistor (which is formed by the source region, the body region and the drain region), the voltage drop which is generated by the holes can result in the parasitic npn transistor being switched on. This can in turn lead to destruction of the trench transistor.